Semiconductor device and a method of fabricating the same

ABSTRACT

A power MOSFET comprises: a semiconductor substrate  21  of a first conduction type; a drain layer  22  of the first conduction type and formed on a surface layer of the substrate; a gate insulating film  25  formed in a partial region on the drain layer  22;  a gate electrode  26  formed on the gate insulating film  25;  an insulating film  27  formed on the gate electrode; a side wall insulator  28  formed on side walls of the gate insulating film  25,  the gate electrode  26,  and the insulating film  27;  a recess formed on the drain layer  22  and in a region other than a region where the gate electrode  25  and the side wall insulator  28  are formed; a channel layer  23  of a second conduction type opposite to the first conduction type and formed in a range from the region where the recess is formed to a vicinity of the region where the gate electrode  26  is formed; a source region layer  24  of the one conduction type and formed on the channel layer  23  outside the recess; and a wiring layer  29  formed to cover the channel layer  23  which is exposed through the recess, the side wall insulator  28,  and the insulating film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod of fabricating it, and more particularly to reduction of thenumber of mask steps in a process of fabricating a power MOSFET, and thelike.

[0003] 2. Description of the Related Art

[0004] Hereinafter, a power MOSFET of the prior art will be describedwith reference to the drawings. FIG. 19 is a section view showing thestructure of a planar type power MOSFET of the prior art.

[0005] In the power MOSFET, as shown in FIG. 19, a drain layer 2consisting of an n− epitaxial layer is formed on an n+ semiconductorsubstrate 1, and a channel layer 3 is formed in a part of the drainlayer by diffusion of a p-type impurity. A body region layer 5 is formedat the center of the channel region by diffusing a p+ impurity. A sourceregion layer 4 which is formed by diffusion of an n+ impurity isdisposed in the surface layer of the channel layer 3 so as to surroundthe body region layer.

[0006] A gate insulating film 6 and a gate electrode 7 are sequentiallyformed on the channel layer 3 so as to overlap with a part of thechannel layer 3 and the source region layer 4. A PSG (Phospho-SilicateGlass) film 8 is formed so as to cover the gate insulating film and thegate electrode. In the PSG film 8, an opening is formed in the regionwhere the body region layer 5 is formed and a part of the region wherethe source region layer 4 is formed. The body region layer 5 and thepart of the source region layer 4 are partly exposed. A wiring layer 9for contact to the body region layer 5 and a part of the source regionlayer 4 is formed so as to cover the layers and the PSG film 8.

[0007] The steps of fabricating the power MOSFET will be described withreference to FIGS. 20 to 25.

[0008] First, the n− drain layer 2 is formed on the n+ semiconductorsubstrate 1 by epitaxial growth. Next, a thick oxide film is formed onthe drain layer, and a photolithography process selectively forms aresist film. A patterning process is conducted on the thick oxide filmwith using the resist film as a mask, and then an oxide film, which willbe formed as the gate insulating film is again formed. Although thethick oxide film is not shown in any of FIGS. 20 to 25, the thick oxidefilm is required in a region where a bonding pad is to be formed.

[0009] Thereafter, a polysilicon layer is formed on the entire surfaceof the semiconductor substrate, a photoresist film is formed, and then apatterning process is conducted by the photolithography method. Thepolysilicon layer and the oxide film are etched with using the patternedresist film as a mask, so that the gate insulating film 6 and the gateelectrode 7 are formed as shown in FIG. 20.

[0010] Next, a p-type impurity is injected with using the gateinsulating film 6 and the gate electrode 7 as a mask, to form thechannel layer 3 on the drain layer 2 as shown in FIG. 21.

[0011] As shown in FIG. 22, a photoresist is then applied to the entiresurface, and a patterning process is conducted by the photolithographymethod so that an opening is formed in a part of the channel layer 3. Ap-type impurity is injected into the channel layer 3 with using thepatterned resist film PR1 as a mask, to form the body region layer 5.

[0012] As shown in FIG. 23, the patterned resist film PR1 is thenremoved away, a photoresist is again applied to the entire surface, andthen patterned by the photolithography method so that a resist film PR2is formed on the region where the body region layer 5 is formed, and ann-type impurity is thereafter injected into the channel layer 3 withusing the resist film PP2, the gate electrode 6, and the like as a mask.

[0013] Thereafter, the PSG film 8 is formed on the entire surface asshown in FIG. 24. A photoresist (not shown) is again applied and theresist is patterned by the photolithography method so that an opening isformed on the body region layer 5 and a part of the source region layer4.

[0014] Next, the PSG film 8 is etched with using the resist as a mask toexpose the regions of the body region layer 5 and a part of the sourceregion layer 4 (FIG. 25).

[0015] A film of a metal such as aluminum is then formed on the entiresurface by sputtering or vapor deposition. A resist film is formed, andthen patterned by the photolithography method. The metal film is etchedaway with using the patterned resist film as a mask to form the wiringlayer 9, thereby completing the power MOSFET having the structure shownin FIG. 19.

[0016] In the above, a planar type power MOSFET has been described. As apower MOSFET of another kind, known is a trench type power MOSFET inwhich a trench is formed in a substrate and a gate electrode is embeddedin the trench.

[0017] Hereinafter, a trench type power MOSFET will be described withreference to FIG. 26.

[0018] As shown in FIG. 26, the power MOSFET comprises a semiconductorsubstrate 11, an n− drain layer 12 which is formed on the substrate byepitaxial growth, and a p-type channel layer 13.

[0019] In a part of the channel layer 13 and the drain layer 12, atrench which passes through the layers is formed. A gate insulating film16 made of an oxide film or the like is formed on the inner face of thetrench. A gate electrode 17 made of polysilicon or the like is formed soas to fill the trench.

[0020] A source region layer 15 of an n+ impurity is formed in thesurface of the channel layer 13 so as to be on both the sides of thegate electrode 17. A p+ body region layer 14 is formed at a centerportion of the source region layer 15.

[0021] A PSG film 18 is formed so as to cover the gate electrode 17. Anopening is formed in a part of the PSG film 18. The body region layer14, and a part of the source region layer 15 which surrounds the bodyregion layer are exposed through the opening. A wiring layer 19 forcontact to the body region layer 14 and the part of the source regionlayer 15, is formed on the layers and the PSG film 18.

[0022] For the above-described planar type power MOSFET, a photomask fora photolithography process for patterning is required in each of thefollowing steps:

[0023] 1) the step of forming the mask for forming the thick oxide filmfor the bonding pad,

[0024] 2) the step of forming the patterning mask for forming the gateelectrode (FIG. 20),

[0025] 3) the step of forming the resist mask for forming the bodyregion 5 (FIG. 22),

[0026] 4) the step of forming the resist mask for forming the sourceregion 4 (FIG. 23),

[0027] 5) the step of forming the resist mask in the case where thecontact hole of the source region 4 is formed in the PSG film 8 (FIG.25), and

[0028] 6) the step of forming the resist mask for patterning the wiringlayer.

[0029] As a result, six photomasks are required in total.

[0030] Therefore, problems in that the number of mask steps andaccompanying steps is very large, that the production process iscomplicated, and that the production cost is high are produced.

[0031] In the production process of a trench type power MOSFET, a bodyregion layer and a source region layer are formed with using aphotoresist as a mask. Therefore, the fine patterning is limited and itis difficult to increase the cell density.

SUMMARY OF THE INVENTION

[0032] The invention has been conducted in view of the defects of theprior art. The object of the invention is to provide a power MOSFETDevice with a high cell density.

[0033] Another object of the invention is to reducing the number ofsteps in a process fabricating a power MOSFET

[0034] The object can be attained by the following configurations.

[0035] As shown in FIG. 1, a first aspect of the present invention is adevice of a semiconductor device, which comprises: a semiconductorsubstrate of a firstconduction type; a drain layer of the firstconduction type and formed on a surface layer of the semiconductorsubstrate; a gate insulating film formed in a partial region on thedrain layer; a gate electrode formed on the gate insulating film; aninsulating film formed on the gate electrode; a side wall insulatorformed on side walls of the gate insulating film, the gate electrode,and the insulating film; a recess formed on the drain layer and in aregion other than a region where the gate electrode and the side wallinsulator are formed; a channel layer of an opposite conduction type andformed in a range from the region where the recess is formed to avicinity of the region where the gate electrode is formed; a sourceregion layer of the one conduction type and formed on the channel layerin a region outside the recess; and a wiring layer formed to cover thechannel layer which is exposed through the recess, the side wallinsulator, and the insulating film.

[0036] A second aspect of the present invention is a device ofsemiconductor device, which comprises: a semiconductor substrate of oneconduction type; a drain layer of the one conduction type and formed ona surface layer of the semiconductor substrate; a channel layer of anopposite conduction type and formed on the drain layer; a trench whichpasses through the channel layer to reach the drain layer; a gateinsulating film formed in a region from an inner wall of the trench tothe channel layer in the periphery of a region where the trench isformed; a gate electrode formed on the gate insulating film to fill thetrench; an insulating film formed on the gate electrode; a side wallinsulator formed on side walls of the gate insulating film, the gateelectrode, and the insulating film; a recess formed on a part of thechannel layer in a region other than a region where the gate electrodeand the side wall insulator are formed; a source region layer formed onthe channel layer in a region outside the recess; a body region layerformed on the channel layer which is below a region where the recess isformed; and a wiring layer formed to cover the source region layer, thebody region layer, the side wall insulator, and the insulating film.

[0037] A third aspect of the present invention is a method offabricating a semiconductor device comprises the steps of: forming adrain layer of one conduction type on a surface layer of a semiconductorsubstrate of the one conduction type; forming a first insulating film onthe drain layer; forming a conductive layer on the first insulatingfilm; forming a second insulating film on the conductive layer;patterning the second insulating film, the conductive layer, and thefirst insulating film, to form a gate insulating film from the firstinsulating film, and a gate electrode from the conductive layer;implanting an impurity of an opposite conduction type into a surfacelayer of the drain layer with using the gate electrode as a mask,thereby forming a channel region layer; implanting an impurity of theone conduction type into the channel region layer with using the gateelectrode as a mask, thereby forming a one conduction type impurityregion layer; forming a third insulating film which covers a surface ofthe one conduction type impurity region layer, side walls of the gateinsulating film, the gate electrode, and the second insulating film, andan upper face of the second insulating film. etching back the thirdinsulating film to form a side wall insulator consisting of the thirdinsulating film, on side walls of the gate insulating film, the gateelectrode, and the second insulating film, and etching the oneconduction type impurity region layer to form a recess, thereby forminga source region layer consisting of a part of the one conduction typeimpurity region layer; and forming a metal layer on an entire surface,and patterning the metal layer, thereby forming a wiring layer.

[0038] A fourth aspect of the present invention is method of fabricatinga semiconductor device comprises the steps of: forming a drain layer ofone conduction type on a surface layer of a semiconductor substrate ofthe one conduction type, and then diffusing an impurity of an oppositeconduction type into a whole surface layer of the drain layer, therebyforming a channel layer; forming a plurality of trenches which passthrough the channel layer to reach the drain layer; forming a firstinsulating film on an inner wall of each of the trenches and a surfaceof the channel layer; forming a conductive layer on the first insulatingfilm; forming a second insulating film on the conductive layer;patterning the second insulating film, the conductive layer, and thefirst insulating film with using a same mask, to form a gate insulatingfilm from the first insulating film, and a gate electrode from theconductive layer; implanting an impurity of the one conduction type intoa surface layer of the channel layer with using the gate electrode as amask, thereby forming a one conduction type impurity region layer;forming a third insulating film on an entire surface; etching back thethird insulating film to form a side wall insulator which covers sidewalls of the gate insulating film, the gate electrode, and the firstinsulating film; applying a photoresist on an entire surface, performingexposure and developing processes to form an opening at a center portionof the one conduction type impurity region layer, and performing anetching process with using the resist film as a mask, thereby forming arecess which passes through the center portion of the one conductiontype impurity region layer and reaches the channel layer, and forming asource region layer consisting of a part of the one conduction typeimpurity region layer; implanting an impurity of the opposite conductiontype into a lower portion of the recess, with using the resist film as amask, thereby forming a body region layer; and removing the resist film,forming a metal layer which covers the source region layer, the bodyregion layer, the side wall insulator, and the second insulating film,and patterning the metal layer, thereby forming a wiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039]FIG. 1 is a section view illustrating the structure of a planartype power MOSFET according to a first embodiment of the invention.

[0040]FIG. 2 is a section view illustrating a method of fabricating thepower MOSFET according to the first embodiment of the invention.

[0041]FIG. 3 is a section view illustrating the method of fabricatingthe power MOSFET according to the first embodiment of the invention.

[0042]FIG. 4 is a section view illustrating the method of fabricatingthe power MOSFET according to the first embodiment of the invention.

[0043]FIG. 5 is a section view illustrating the method of fabricatingthe power MOSFET according to the first embodiment of the invention.

[0044]FIG. 6 is a view illustrating the structure of a planar type powerMOSFET according to a second embodiment of the invention.

[0045]FIG. 7 is a section view illustrating a method of fabricating thepower MOSFET according to the second embodiment of the invention.

[0046]FIG. 8 is a section view illustrating the method of fabricatingthe power MOSFET according to the second embodiment of the invention.

[0047]FIG. 9 is a section view illustrating the method of fabricatingthe power MOSFET according to the second embodiment of the invention.

[0048]FIG. 10 is a section view illustrating the method of fabricatingthe power MOSFET according to the second embodiment of the invention.

[0049]FIG. 11 is a section view illustrating the method of fabricatingthe power MOSFET according to the second embodiment of the invention.

[0050]FIG. 12 is a view illustrating the structure of a trench typepower MOSFET according to a third embodiment of the invention.

[0051]FIG. 13 is a section view illustrating a method of fabricating thepower MOSFET according to the third embodiment of the invention.

[0052]FIG. 14 is a section view illustrating the method of fabricatingthe power MOSFET according to the third embodiment of the invention.

[0053]FIG. 15 is a section view illustrating the method of fabricatingthe power MOSFET according to the third embodiment of the invention.

[0054]FIG. 16 is a section view illustrating the method of fabricatingthe power MOSFET according to the third embodiment of the invention.

[0055]FIG. 17 is a section view illustrating the method of fabricatingthe power MOSFET according to the third embodiment of the invention.

[0056]FIG. 18 is a section view illustrating the method of fabricatingthe power MOSFET according to the third embodiment of the invention.

[0057]FIG. 19 is a section view illustrating the structure of a planartype power MOSFET of the prior art.

[0058]FIG. 20 is a section view illustrating a method of fabricating thepower MOSFET of the prior art.

[0059]FIG. 21 is a section view illustrating the method of fabricatingthe power MOSFET of the prior art.

[0060]FIG. 22 is a section view illustrating the method of fabricatingthe power MOSFET of the prior art.

[0061]FIG. 23 is a section view illustrating the method of fabricatingthe power MOSFET of the prior art.

[0062]FIG. 24 is a section view illustrating the method of fabricatingthe power MOSFET of the prior art.

[0063]FIG. 25 is a section view illustrating the method of fabricatingthe power MOSFET of the prior art.

[0064]FIG. 26 is a section view illustrating the structure of a trenchtype power MOSFET of the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0065] First Embodiment

[0066] Hereinafter, a planar type power MOSFET according to a firstembodiment of the invention will be described with reference to theaccompanying drawings.

[0067]FIG. 1 is a section view showing the structure of a planar typepower MOSFET according to the embodiment. In the specification, ann-channel transistor will be described as an example. The embodiment canbe applied also to a p-channel transistor.

[0068] In the power MOSFET, as shown in FIG. 1, a drain layer 22consisting of an n− epitaxial layer is formed on an n+ semiconductorsubstrate 21. A gate insulating film 25, a gate electrode 26, and an NSGfilm 27 are sequentially formed in a part of the drain layer 22.

[0069] A side wall insulator 28 which similarly consists of an NSG filmis formed on side walls of the gate insulating film 25, the gateelectrode 26, and the NSG film 27.

[0070] A channel layer 23 is formed by diffusion of a p-type impurity onthe epitaxial layer 22 and on both the sides of the region where thegate insulating film 25, the gate electrode 26, and the NSG film 27 areformed. A recess in which end portions respectively coincide with sideends of the side wall insulator 28 is formed at a center portion of thechannel layer 23. An n+ source region layer 24 is formed so as tosurround the recess.

[0071] A wiring layer 29 consisting of a film of a metal such asaluminum is formed so as to cover the channel layer 23, the side wallinsulator 28, and the NSG film 27 in the recess, thereby enabling acontact to the source region layer 24 to be established.

[0072] Hereinafter, a method of fabricating the power MOSFET having theabove-described structure will be described with reference to thedrawings. FIGS. 2 to 5 are section views illustrating the method offabricating the power MOSFET according to the embodiment.

[0073] First, the n− drain layer 22 is formed on the n+ semiconductorsubstrate 21 by epitaxial growth. Next, a thick oxide film having athickness of about 5,000 to 10,000 A is formed on the drain layer, and aphotolithography process selectively forms a resist film. The oxide filmis patterned by etching with using the resist film as a first mask.Although the thick oxide film is not shown in any of FIGS. 2 to 5, thethick oxide film is required in a region where a bonding pad will beformed later. Thereafter, an oxide film 25A which will be formed as thegate insulating film is again grown.

[0074] Thereafter, a polysilicon layer 26A having a thickness of about5,000 A is formed on the upper entire surface of the oxide film, and theNSG film 27 having a thickness of about 5,000 to 10,000 A is then formedon the entire surface. A photoresist is applied to the entire surface,and then patterning is performed by exposure and developing processes,thereby forming a resist film PR. As a result of the steps describedabove, the structure of FIG. 2 in which the patterned resist film PR isformed on the upper face is obtained.

[0075] Next, the NSG film 27, the polysilicon layer 26A, and the oxidefilm 25A are subjected to dry etching with using the patterned resistfilm PR as a mask, so that the gate insulating film 25 and the gateelectrode 26 are simultaneously formed as shown in FIG. 3.

[0076] Thereafter, boron which is a p-type impurity is injected withusing the gate insulating film 25 and the gate electrode 26 as a maskand under conditions of a dose amount of 5×10¹³/cm² and an accelerationvoltage of 80 keV, thereby forming the channel layer 23 on the n−epitaxial layer 22.

[0077] In succession to this step, as which is an n-type impurity isinjected with using the gate insulating film 25 and the gate electrode26 as a mask and under conditions of a dose amount of 1×10¹⁶/cm² and anacceleration voltage of 140 keV, thereby forming an n+ impuritydiffusion layer 24A an the surface.

[0078] Next, an NSG film 28A having a thickness of 8,000 A is formed onthe entire surface. As a result of the steps described above, thestructure of FIG. 4 is obtained.

[0079] Thereafter, the entire surface is etched back by anisotropicetching.

[0080] As a result of this step, the side wall insulator 28 is formed onthe side walls of the gate insulating film 25, the gate electrode 26,and the NSG film 27, and at the same time a part of the channel layer 23is etched, with the result that a recess OB having a depth of about 0.2to 0.6 μm is formed in the layer.

[0081] The formation of the recess OB causes the n+ impurity diffusionlayer 24A to form the source region layer 24 penetrated by the recessOB, as shown in FIG. 5, and the source region layer 24 to besimultaneously formed.

[0082] Thereafter, boron is implanted under conditions of 35 keV and5×10¹⁵/cm² to form a p+ body contact 23A.

[0083] Next, a film of a metal such as aluminum and having a thicknessof about 3 μm is formed on the entire surface by vapor deposition orsputtering, and then patterned, thereby completing the planar type powerMOSFET shown in FIG. 1.

[0084] In the method of fabricating a semiconductor device according tothe embodiment, the NSG film 27 is formed on the gate electrode 26, theNSG film 28A is then formed on the entire surface, the NSG film isetched back to form the side wall insulator 28, and the recess OB isformed in the epitaxial layer 22, thereby forming the source regionlayer 24. Therefore, a photomask step which, in the prior art, must beconducted in the patterning for forming the source region 24 is notrequired.

[0085] In the entire process of the first embodiment of the invention, aphotomask is required only in the following three steps:

[0086] 1) the step of forming the mask for forming the thick oxide filmfor the initial bonding pad,

[0087] 2) the step of forming the patterning mask for forming the gateelectrode (FIG. 2), and

[0088] 3) the step of forming the mask for forming the wiring layer.

[0089] In the embodiment, as described above, it is required to use onlythe three photomasks in total. Unlike the prior art in which sixphotomasks are used, the problems in that the number of mask steps andaccompanying steps is very large, that the production process iscomplicated, and that the production cost is high can be suppressed.Although it is sometimes required to use one more mask for forming agate contact, the number of the total mask is reduced. Further pluralityof the power MOSFETs can be integrated on a cell region of a substratein a matrix structure.

[0090] Further, according to the first embodiment, since the recess isformed so as to be coincided with the end of the side wall insulator 38,a length between the source contact region and channel region is reducedand as a result, ON-resistance of the power MOSFET is reduced.

[0091] Second Embodiment

[0092] Hereinafter, a second embodiment of the invention will bedescribed with reference to the accompanying drawings.

[0093]FIG. 6 is a section view illustrating the structure of a planartype power MOSFET according to the second embodiment of the invention.

[0094] As shown in FIG. 6, the power MOSFET according to the secondembodiment of the invention is very similar in structure to the powerMOSFET of the first embodiment which has been described with respect toFIG. 1. The embodiment is different from the first embodiment in that ap+ body region 40 is formed in a source region layer 34, that the sourceregion layer 34 is wider than the source region layer of the firstembodiment, and that the upper face of the layer is exposed.

[0095] In the power MOSFET according to the second embodiment of theinvention, as shown in FIG. 6, an n− epitaxial layer 32 is formed on ann+ semiconductor substrate 31. A gate insulating film 35, a gateelectrode 36, and an NSG film 37 are secuentially formed in a part ofthe epitaxial layer 32.

[0096] A side wall insulator 38 which similarly consists of an NSG filmis formed on side walls of the gate insulating film 35, the gateelectrode 36, and the NSG film 37.

[0097] A channel layer 33 is formed by diffusion of a p-type impurity onthe epitaxial layer 32 and on both the sides of the region where thegate insulating film 35, the gate electrode 36, and the NSG film 37 areformed. A recess in which end portions respectively are disposed insideof side ends of the side wall insulator 38 is formed at a center portionof the channel layer 33. An n+ source region layer 34 is formed so as tosurround the recess.

[0098] A wiring layer 39 consisting of a film of a metal such asaluminum is formed so as to cover the channel layer 33, the side wallinsulator 38, and the NSG film 37 in the recess, thereby enabling acontact to the source region layer 34 to be established.

[0099] Hereinafter, a method of fabricating the power MOSFET having theabove-described structure will be described with reference to thedrawings. FIGS. 7 to 11 are section views illustrating the method offabricating the power MOSFET according to the embodiment.

[0100] First, the n− epitaxial layer 32 is formed on the n+semiconductor substrate 31 by epitaxial growth. Next, a thick oxide filmis formed on the epitaxial layer, and then patterned. Thereafter, anoxide film which will be formed as the gate insulating film is againgrown. Although the thick oxide film is not shown in any of FIGS. 7 to11, the thick oxide film is required in a region where a bonding pad isto be formed.

[0101] Thereafter, a polysilicon layer is formed on the whole of theupper face, and an NSG film is formed on the entire surface. Aphotoresist is applied to the entire surface, and then patterning isperformed by exposure and developing processes.

[0102] Next, the NSG film 37, the polysilicon layer 36A, and the oxidefilm 35A are patterned by etching with using the patterned resist filmPR as a mask, so that the gate insulating film 35 and the gate electrode36 are simultaneously formed as shown in FIG. 7 and the NSG film 37having the same pattern as the gate insulating film and the gateelectrode is obtained.

[0103] Thereafter, a p-type impurity is injected with using the gateinsulating film 35 and the gate electrode 36 as a mask, thereby formingthe p-type channel layer 33 on the n− epitaxial layer 32 as shown inFIG. 8. In succession to this step, an n-type impurity is injected withusing the gate insulating film 35 and the gate electrode 36 as a mask,thereby forming an n+ impurity diffusion layer 34A in the surface.

[0104] Next, an NSG film 38A is again formed on the entire surface, anda photoresist is applied to the entire surface. Then, patterning isperformed by exposure and developing processes with using the photomask,thereby forming an opening in the resist PR in the region where the bodyregion 40 will be formed later (FIG. 9).

[0105] The n+ impurity diffusion layer 34A formed on the surface ofepitaxial layer 32 is etched away with using the resist PR as a mask,thereby forming a recess OB2. As a result, the region layer 34 isformed. Thereafter, a p-type impurity is injected into the recess OB2 toform the body region 40 (FIG. 10).

[0106] Thereafter, the resist is removed away and the entire surface isetched back by anisotropic etching. As a result of this step as shown inFIG. 11, the side wall insulator 38 is formed on the side walls of thegate insulating film 35, the gate electrode 36, and the NSG film 37, andat the same time the source region 34 is exposed. And then if required,gate contact region is formed (not shown).

[0107] Next, a film of a metal such as aluminum is formed on the entiresurface by vapor deposition or sputtering, and then patterned, therebycompleting the planar type power MOSFET shown in FIG. 6.

[0108] In the method of fabricating a semiconductor device according tothe embodiment, the NSG film 37 is formed on the gate electrode 36, theNSG film 38A is then formed on the entire surface, the NSG film isetched back to form the side wall insulator 38, and the recess OB2 forforming the body region is formed in the epitaxial layer 32, therebyforming the source region layer 34. Therefore, a photomask step which,in the prior art, must be conducted in the patterning for forming thesource region is not required.

[0109] In the entire process of the second embodiment of the invention,a photomask is required only in the following four steps:

[0110] 1) the step of forming the mask for forming the thick oxide filmfor the initial bonding pad,

[0111] 2) the step of forming the patterning mask for forming the gateelectrode (FIG. 7),

[0112] 3) the step of forming the mask for forming the recess forforming the body region (FIG. 9), and

[0113] 4) the step of forming the mask for forming the wiring layer.

[0114] In the embodiment, as described above, it is required to use onlythe four photomasks in total. Unlike the prior art in which sixphotomasks are used, the problems in that the number of mask steps andaccompanying steps is very large, that the production process iscomplicated, and that the production cost is high can be suppressed.

[0115] The conditions such as thickness of the films in the secondembodiment are identical with those of the first embodiment, and hencetheir description is omitted. Further plurality of the power MOSFETs canbe integrated on a cell region of a substrate in a matrix structure.

[0116] Further, according to the second embodiment, since the recess isselectively formed at a center portion on a surface of the sourceregion, a contact area of the wiring layer contact with the sourceregion is sufficiently large and as a result, ON-resistance of the powerMOSFET is reduced and an endure against avalanche is improved.

[0117] Third Embodiment

[0118] Hereinafter, a power MOSFET having a trench structure accordingto the embodiment of the invention will be described with reference tothe accompanying drawings. FIG. 12 is a section view illustrating thestructure of the power MOSFET according to the embodiment.

[0119] First, the structure of the power MOSFET will be described.

[0120] In the power MOSFET, as shown in FIG. 12, an n− drain layer 42 isformed by epitaxial growth on a semiconductor substrate 41 made of n+silicon. A channel layer 43 consisting of a p+ impurity diffusion layeris formed on the surface layer of the drain layer 42. In thesemiconductor substrate 41, trench which passes through the channellayer 43 to reach to the drain layer 42 on the substrate are formed.(The channel layer 43 can be formed by epitaxtial growth.) A gateinsulating film 46 made of a silicon oxide film having a thickness ofabout 500 A is formed on the surface of each trench.

[0121] A gate electrode 47 made of polysilicon is formed on the gateinsulating film 46 so as to fill the trench.

[0122] A recess is formed in a part of the surface layer of the channellayer 43 which is penetrate into plural portions by the trench. A sourceregion layer 45 consisting of an n+ impurity diffusion layer is formedon the channel layer 43 and so as to surround the recess. A body regionlayer 44 consisting of a p+ impurity diffusion layer is formed in thechannel layer 43 below the recess. The source region layer may be formedbefore the formation of the trench.

[0123] An NSG film 48 having the same pattern as the gate electrode 47is formed so as to cover the upper portion of the gate electrode 47.Furthermore, a side wall insulator 49 which also is made of an NSG filmis formed on the side walls of the NSG film 48, the gate electrode 47,and the gate insulating film 46.

[0124] A wiring layer 50 consisting of a film of a metal such asaluminum and having a thickness of about 3 μm is formed so as to coverthe NSG film 48, the side wall insulator 49, the exposed source regionlayer 45, and the body region layer 44.

[0125] Hereinafter, a method of fabricating the trench type power MOSFETwill be described with reference to the drawings. FIGS. 13 to 18 aresection views illustrating the method of fabricating the power MOSFETaccording to the embodiment.

[0126] First, the n− drain layer 42 is formed on the n+ semiconductorsubstrate 41 by epitaxial growth. Next, boron which is a p+ impurity isinjected into the entire surface of the surface layer of the drain layer42 under conditions of a dose amount of 5×10¹³/cm², thereby forming thechannel layer 43. The channel layer 43 can be formed by epitaxialgrowth.

[0127] Next, a resist mask is formed, and an etching process isperformed with using it as a mask, thereby forming the trench whichpasses through the channel layer 43 to reach the drain layer 42.

[0128] The entire surface is then oxidized to form the gate insulatingfilm 46 which extends over from the surface of the channel layer 43 tothe inner wall of trench. A polysilicon layer 47A is formed on the upperface of the film by the CVD method so as to have a thickness of about5,000 A.

[0129] Thereafter, an NSG film 48 is formed on the entire surface,thereby obtaining the structure of FIG. 13.

[0130] Next, a photoresist is applied to the entire surface, andpatterning is performed by exposure and developing processes, therebycausing the photoresist to selectively remain on the NSG film 48 in theregion including that where the trench is formed. The polysilicon layer47A and the NSG film 48 are etched away with using the photoresist as amask to form the gate electrode 47. Next, an n+ impurity is injectedinto the channel layer 43 with using the gate electrode as a mask,thereby forming an n-type impurity region layer 45A (FIG. 14).

[0131] As shown in FIG. 15, thereafter, an NSG film 49A having athickness of 8,000 A is formed on the entire surface.

[0132] As shown in FIG. 16, the entire surface is etched back to formthe side wall insulator 49 on the side walls of the gate electrode 47and the NSG film 48.

[0133] A photoresist is applied to the entire surface and thenpatterned, thereby forming a resist mask PR in which an opening OP isformed at the center of the n+ impurity region layer 45A as shown inFIG. 17. The n+ impurity region layer 45A is etched with using theresist mask as a mask, to form a recess which passes through the layer.

[0134] A p-type impurity is injected into the entire surface while theresist mask PR remains to exist, so that the body region layer 44consisting of the p+ impurity diffusion region is formed below therecess as shown in FIG. 18.

[0135] The resist mask PR is then removed away, a film of a metal suchas aluminum is formed on the entire surface, and the metal film ispatterned, with the result that the trench type power MOSFET having thestructure of FIG. 12 is formed.

[0136] According to the method of fabricating a trench type power MOSFETof the embodiment, unlike the prior art, none of resist masks are usedwhen the source region and the body region are to be formed, and, thebody region is formed by selectively etching the n+ impurity regionlayer to be source region 45, forming a trench which reaches to thechannel region 43, and injecting a p+ impurity into the bottom of thetrench.

[0137] Therefore, fine patterning can be performed. This produces anadvantage that the cell density can be further increased.

[0138] In the entire process of the production method, a photomask isrequired only in the following four steps:

[0139] 1) the step of forming the patterning mask for forming thetrench,

[0140] 2) the step of forming the patterning mask for forming the gateelectrode (FIG. 14),

[0141] 3) the step of forming the mask for forming the recess forforming the body region (FIG. 17), and

[0142] 4) the step of forming the mask for forming the wiring layer.

[0143] Therefore, the problems in that the number of mask steps andaccompanying steps is very large, that the production process iscomplicated, and that the production cost is high can be suppressed asmuch as possible.

[0144] In the first to third embodiments, the gate electrode is made ofpolysilicon. The invention is not restricted to polysilicon.Alternatively, for example, polycide or a metal may be used. Furtherplurality of the power MOSFETs can be integrated on a cell region of asubstrate in a matrix structure. In the structure, one of gate electrodeor source region is formed in a lattice structure, and the other isformed so as to be a plurality of independent regions.

[0145] Furthermore, it is a matter of course that the conditions such asthe thickness of various films and the like are not limited to theabove-mentioned values.

[0146] As described above, according to the method of fabricating asemiconductor device of the invention, an impurity of a secondconduction type is implanted into a surface layer of the drain layer ofthe first conduction type with using a gate electrode as a mask, therebyforming a channel region layer, an impurity of a first conduction typeis introduced(implanted) into the channel region layer with using thegate electrode as a mask, thereby forming a impurity region of the firstconduction type, a third insulating film which covers the surface of theimpurity region side walls of the gate insulating film, the gateelectrode, and the second insulating film, and the upper face of thesecond insulating film is formed, the third insulating film is etchedback to form a side wall insulator consisting of the third insulatingfilm, on side walls of the gate insulating film, the gate electrode, andthe second insulating film, and impurity region is etched to form arecess, thereby forming a source region layer consisting of a part ofthe impurity region.

[0147] Therefore, in the photolithography process of forming a resistmask for patterning, only three photomasks are required for thefollowing steps:

[0148] 1) the step of forming the mask for forming the thick oxide filmfor the initial bonding pad formed on a peripheral portion of thesubstrate

[0149] 2) the step of forming the patterning mask for forming the gateelectrode, and

[0150] 3) the step of forming the mask for forming the wiring layer.

[0151] According to this configuration, as compared with the prior artproduction method in which six photomasks are used in the production ofa planar type power MOSFET, the number of mask steps and accompanyingsteps can be largely reduced, the labor of the production process can bereduced, and the production cost can be largely lowered.

[0152] According to the other method of fabricating a semiconductordevice of the invention, an impurity of a first conduction type isimplanted into the channel region layer with using the gate electrode asa mask, thereby forming a impurity region of the first conduction type,a third insulating film is formed on the entire surface, the thirdinsulating film is etched back to form a side wall insulator whichcovers side walls of the gate insulating film, the gate electrode, and afirst insulating film, a photoresist is applied to the entire surface,exposure and developing processes are performed to form an opening at acenter portion of the impurity region, an etching is performed withusing the resist film as a mask to form a recess which passes throughthe center portion of the impurity region and reaches a channel layer,and a source region layer consisting of a part of the impurity region,an impurity of a second conduction type opposite to the first conductiontype is implanted into a lower portion of the recess, with using theresist film as a mask, thereby forming a body region layer, and theresist film is removed away.

[0153] Therefore, in the photolithography process of forming a resistmask for patterning, only four photomasks are required for the followingsteps:

[0154] 1) the step of forming the patterning mask for forming thetrench,

[0155] 2) the step of forming the patterning mask for forming the gateelectrode,

[0156] 3) the step of forming the mask for forming the recess forforming the body region, and

[0157] 4) the step of forming the mask for forming the wiring layer.

[0158] According to this configuration, as compared with the prior artproduction method in which six photomasks are used, in a production of atrench type power MOSFET, a photomask step and accompanying steps can beomitted. Therefore, the problems of the prior art in that the productionprocess is complicated, and that the production cost is high can besuppressed as much as possible.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate of a first conduction type; a drain layer of thefirst conduction type, formed on a surface of said semiconductorsubstrate; a channel region of a second conduction type opposite to thefirst conduction type which is formed on said drain region a sourceregion formed of the first conduction type, in said channel region; agate insulating film formed on said channel region; a gate electrodeformed on said gate insulating film; a recess formed in said sourceregion so as to penetrate the source region and reach the channelregion; an insulating layer formed on a upper and side wall surfaces ofthe gate electrode; and a wiring layer contacted with said source regionand formed on the insulating layer.
 2. The semiconductor deviceaccording to the claim 1, further comprising a body contact region ofthe second conduction type, formed in a part of the channel regionexposed in a bottom surface of the recess, wherein the wiring layer iscontacted with said body contact region and said source region.
 3. Thesemiconductor device according to the claim 1, wherein the insulatinglayer is constituted by an upper insulating layer and a side wallinsulator, the recess is formed in align with the edge of the side wallinsulator.
 4. The semiconductor device according to the claim 3, whereinthe body contact region is separated from the source region.
 5. Thesemiconductor device according to the claim 1, further comprising atrench formed in said channel region, wherein said gate insulating filmis formed on an inner wall of the trench and on the substrate mainsurface, and said gate electrode is embedded in the trench and reach tothe substrate main surface.
 6. The semiconductor device according to theclaim 5, wherein the insulating layer is constituted by an upperinsulating layer and a side wall insulator, the recess is formed inalign with the edge of the side wall insulator.
 7. The semiconductordevice according to the claim 6, wherein the body contact region isseparated from the source region.
 8. The semiconductor device accordingto the claim 5, wherein said channel region is formed on the entiresurface of the drain layer.
 9. The semiconductor device according to theclaim 8, wherein the recess is selectively formed in a center portion ofthe source region and penetrate the source region.
 10. Thesemi-conductor device according to the claim 1, wherein said sourceregion is constituted by plurality of regions respectively located in amatrix, and said gate electrode is formed in a lattice-like shape tosurround the source regions.
 11. The semiconductor device according tothe claim 4, wherein the trench comprises a plurality of trenches formedin a matrix so as to be surrounded said source region.
 12. A method offabricating a semiconductor device, comprising the steps of: forming adrain layer of a first conduction type on a surface of a semiconductorsubstrate of the first conduction type; forming a first insulating filmon said drain layer; forming a first conductive layer on said firstinsulating film; forming a second insulating film on said conductivelayer; patterning said second insulating film, said conductive layer,and said first insulating film, to form a gate insulating film from saidfirst insulating film, and a gate electrode from said first conductivelayer; implanting an impurity of a second conduction type opposite tothe first conduction type into a surface of said drain layer with usingsaid gate electrode as a mask, thereby forming a channel region of thesecond conduction type; implanting an impurity of the first conductiontype into said channel region with using said gate electrode as a mask,thereby forming a impurity region of the first conduction type forming athird insulating film so as to cover a surface of the impurity region,side walls of said gate insulating film, said gate electrode, and saidsecond insulating film, and an upper face of said second insulatingfilm; etching back said third insulating film to form a side wallinsulator consisting of said third insulating film, by remaining saidthird insulating film selectively on side walls of said gate insulatingfilm, said gate electrode, and said second insulating film; etching theimpurity region to form a recess so as to penetrate the impurity region,thereby forming a source region consisting of the impurity region; andforming a second conductive layer on an entire surface, and patterningsaid second conductive layer, thereby forming a wiring layer.
 13. Themethod of fabricating a semiconductor device, according to the claim 12,wherein further comprising a step of introducing an impurity of thesecond conduction type into the bottom of the recess to form a bodycontact region of the second conduction after etching the impurityregion prior to forming a second conductive layer.
 14. The method offabricating a semiconductor device, according to the claim 12, whereinthe etching step comprises the steps of: forming a mask pattern havingan opening located in a center of the source region and cover an entiresurface except for the opening before etching the impurity region;etching the impurity region by using the mask pattern 8 to form a recessshallower than the exposed surface of the impurity region so as topenetrate the impurity region, thereby forming a source region of theimpurity region remained; and introducing an impurity of the secondconduction type into the bottom of the recess to form a body contactregion of the second conduction.
 15. The method of fabricating asemiconductor device, according to the claim 12, further comprising thesteps of: forming a fourth thick insulating layer on a surface of thesemiconductor substrate; and patterning the fourth thick insulatinglayer so as to remain a peripheral region of the substrate, prior toforming the drain region.
 16. A method of fabricating a semiconductordevice, comprising the steps of: forming a drain layer of a firstconduction type on a surface of a semiconductor substrate of the firstconduction type; introducing an impurity of a second conduction typeopposite to the first conduction type into an entire surface of saiddrain layer, thereby forming a channel layer; forming a trench so as topenetrate said channel layer and reach said drain layer using a firstmask; forming a first insulating film on an inner wall of said trenchand a surface of said channel layer; forming a conductive layer on saidfirst insulating film; forming a second insulating film on saidconductive layer; patterning said second insulating film, saidconductive layer, and said first insulating film with using a samesecond mask, to form a gate insulating film of said first insulatingfilm, and a gate electrode of said conductive layer; implanting animpurity of the first conduction type into a surface of said channellayer with using said gate electrode as a mask, thereby forming aimpurity region of the first conduction type; forming a third insulatingfilm on an entire surface; etching back said third insulating film toform a side wall insulator which covers side walls of said gateinsulating film, said gate electrode, and said first insulating film;forming a third mask having an opening located in a center of the sourceregion and cover an entire surface except for the opening, beforeetching the impurity region; etching the impurity region by using thethird mask to form a recess shallower than the exposed surface of theimpurity region so as to penetrate the impurity region and reach to thechannel region, thereby forming a source region consisting of theimpurity region; and implanting an impurity of the second conductiontype into a bottom of said recess, with remaining said third maskthereby forming a body contact region; and removing said third mask; andforming a second conductive layer which covers said source region, saidbody contact region, said side wall insulator, and said a insulatingfilm, and patterning said second conductive layer by using a fourthmask, thereby forming a wiring layer.
 17. The method of fabricating asemiconductor device according to claim 16, wherein said step of forminga source region is formed before the step of forming a trench.